Power and Signal Integrity Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.

You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.

Design and optimize power distribution networks (PDN) across chip, package, and board levels.

Manage power/ground planes, decoupling capacitors, and power gating strategies.

Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience

4 years of experience with power distribution network (PDN) design, power integrity (PI) simulations, low-power design methodologies, or electrical modeling.

Preferred qualifications:

Experience with industry-standard Electronic Design Automation (EDA) tools for simulation and layout (e.g., Cadence Sigrity/Allegro, Ansys HFSS/PowerDC/Q3D, Keysight ADS, Synopsys HSPICE).

Proficiency in scripting languages such as Python, Perl, or Tcl for flow automation and data analysis.

Familiarity with high-speed testing equipment like VNAs, TDRs, and oscilloscopes for measurement and validation.

Knowledge of circuit analysis, electromagnetics, and transmission line theory

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience

4 years of experience with power distribution network (PDN) design, power integrity (PI) simulations, low-power design methodologies, or electrical modeling.