Senior PD Engineer: Synthesis & STA
Posted Aug 6, 2026·Open for 46 days (and counting)
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Key details
Function
Engineering
Seniority
Mid
Workplace
Hybrid
Location
Bangalore INDIA Hybrid / Remote
Specialty
Synthesis Sta
Job Description
Job Title: Senior PD engineer : Synthesis & STA
Location: Bangalore INDIA Hybrid / Remote
Role Overview
We are seeking a highly skilled VLSI Synthesis & STA Specialist to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.
In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.
You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.
This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.
Key Responsibilities
- Synthesis Ownership: Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.
- Quality Signoff: Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.
- RTL Collaboration: Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.
- Frequency & LOL Optimization: Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.
- Micro-architecture Guidance: Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.
- Role Expansion: Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.
Required Skills & Qualifications
- Experience: 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
- EDA Tools Expertise: Hands-on experience with industry-standard synthesis tools, with a strong preference for Cadence Genus. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.
- Timing & STA: Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
- RTL & Logic Fundamentals: Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
- Netlist Optimization: Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
- Scripting/Automation: Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
- Cross-Functional Communication: Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.
Preferred Qualifications
- Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.
- Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
-
Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.
Audit details(provenance, verification trail, raw fields)
Core fields
Posting ID
encharge-ai:4357591009Title
Senior PD Engineer: Synthesis & STA
Function
Engineering
Location
Bangalore INDIA Hybrid / Remote
Workplace mode
unspecified
Posted at
2026-08-06 16:59:52Z
Compensation
undisclosed
Provenance
First seen (our tracker)
2026-08-07 08:45:57Z
Last seen
2026-09-21 09:01:29Z
Last updated
2026-09-21 09:01:29Z
Removed at
still open
Days open
Open for 46 days (and counting)
ATS adapter
greenhouse
ATS slug
enchargeai36Verification trail
This posting hasn't been probed by our closure verifier yet. Stream C runs on a rolling schedule against postings approaching the close-decision threshold.
LLM enrichment
Enriched at 2026-08-18 02:28:40Z. Enrichment runs once per posting, never re-runs.
Seniority
ic_l4
Role archetype
engineering
Specialty
synthesis_sta
Workplace mode
hybrid
City (normalized)
Bangalore
Country (normalized)
India
Comp range
—
Tech stack
—
Novel role archetype?
no
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