Staff DFT Engineer

<p>EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.</p>
<div class="elementToProof"><strong>The Opportunity</strong></div>
<div class="elementToProof">We are looking for a high-energy,<span class="Apple-converted-space"> </span><strong>Staff-level DFT Engineer</strong> to join our silicon team. In the fast-paced world of Edge AI, efficiency is everything. </div>
<div class="elementToProof">As a "go-getter" in a startup environment, you’ll have the autonomy to shape the end-to-end DFT insertion process for our next-generation AI accelerators.</div>
<div class="elementToProof"><strong>Location: Hybrid via Bangalore or Remote across India </strong></div>
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<div class="elementToProof"><strong>Key Responsibilities:</strong></div>
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<div class="elementToProof"><strong>End-to-End DFT Strategy:</strong> Define and implement the complete DFT architecture as independent as possible, including Scan, MBIST, BSCAN, and Boundary Scan.</div>
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<div class="elementToProof"><strong>Constraint Management:</strong> Take charge of DFT constraint development and management, ensuring seamless integration with synthesis and STA (Static Timing Analysis) teams.</div>
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<div class="elementToProof"><strong>ATPG & Simulation:</strong> Generate high-coverage test patterns (Stuck-at, At-speed, Transition, Path Delay) and lead the verification of these patterns through timing-annotated simulations.</div>
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<div class="elementToProof"><strong>AI-Specific Optimization:</strong> Implement advanced DFT techniques tailored for Edge AI architectures, such as high-bandwidth memory testing and low-power test modes.</div>
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<div class="elementToProof"><strong>Hierarchical DFT:</strong> Design and execute hierarchical DFT flows to manage complexity in large-scale AI SOCs.</div>
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<div class="elementToProof"><strong>Silicon Bring-up:</strong> Partner with the ATE (Automated Test Equipment) teams to debug patterns on silicon and drive yield improvement initiatives.</div>
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<div class="elementToProof"><strong>What You Bring</strong></div>
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<div class="elementToProof"><strong>The Experience:</strong> 9–10 years of hands-on experience in DFT, preferably with at least one full tape-out cycle in a lead or staff capacity.</div>
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<div class="elementToProof"><strong>The Toolkit:</strong> Expert-level proficiency with industry-standard tools (e.g., Siemens Tessent, Synopsys DFTMAX/TetraMAX, or Cadence Genus/Modus).</div>
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<div class="elementToProof"><strong>Technical Depth:</strong> Deep understanding of DFT-centric STA, power-aware DFT, and high-speed IO testing.</div>
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<div class="elementToProof"><strong>Startup Mindset:</strong> You are comfortable wearing multiple hats. You don't wait for a manual; you build the manual.</div>
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<div class="elementToProof"><strong>Edge AI Interest:</strong> A genuine interest in how AI hardware differs from general-purpose CPUs/GPUs.</div>
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<div class="elementToProof"><strong>Why Join Us?</strong></div>
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<div class="elementToProof"><strong>High Impact:</strong> In a startup, your decisions aren't buried in layers of bureaucracy; they are visible in the final silicon.</div>
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<div class="elementToProof"><strong>Growth:</strong> You’ll be working alongside veterans from top-tier chipmakers, solving problems that haven't been solved yet.</div>
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<div class="elementToProof"><strong>Ownership:</strong> We value "intrapreneurs"—engineers who treat the product like it’s their own.</div>
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<div class="elementToProof"><strong>Technical Skills at a Glance</strong></div>
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<div><strong>Category</strong></div>
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<div><strong>Requirement</strong></div>
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<div><strong>Logic Test</strong></div>
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<div>Scan Compression, ATPG (Stuck-at, Transition), EDT</div>
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<div><strong>Memory Test</strong></div>
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<div>MBIST (Programmable/Hardened), Repair Algorithms</div>
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<div><strong>System Level</strong></div>
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<div>JTAG, IEEE 1149.1/6, IEEE 1500 (Wrappers)</div>
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<div><strong>Timing</strong></div>
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<div>DFT Constraints, SDC management, Post-layout STA</div>
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<div><strong>Scripting</strong></div>
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<div>Expert in Tcl, Python, or Perl for flow automation</div>
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</tbody>
</table>
<p> </p>