Staff/Senior Staff Physical Design Engineer (Technical Lead)

<p>EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.</p>
<div class="elementToProof"><strong>Job Title:</strong> <strong>Staff/</strong><strong>Senior Staff Physical Design Engineer (Technical Lead)</strong></div>
<div class="elementToProof"><strong>Experience: </strong>
<div class="elementToProof">Staff 8-10 years</div>
<div class="elementToProof">Senior Staff 11-13 years</div>
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<div class="elementToProof"><strong>Location:</strong>  Bangalore Hybrid/Remote or Remote in India</div>
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<div class="elementToProof"><strong>The Role</strong></div>
<div class="elementToProof">We are seeking a high-impact<span class="Apple-converted-space"> <strong>Staff/</strong></span><strong>Senior Staff Physical Design Engineer</strong> to serve as a Technical Lead for our next-generation silicon products.</div>
<div class="elementToProof">This is a "player-coach" role designed for a<strong><span class="Apple-converted-space"> </span>versatile expert<span class="Apple-converted-space"> </span></strong>who is equally comfortable architecting a  convergence strategy as they are mentoring a small team of engineers.</div>
<div class="elementToProof">You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits of<span class="Apple-converted-space"> </span><strong>PPA (Power, Performance, Area)</strong>.</div>
<div class="elementToProof">As a Staff/Senior Staff lead, you are expected to be the "anchor" of the project—assertive in your decision-making, highly analytical in your debugging,</div>
<div class="elementToProof"> and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise.</div>
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<div class="elementToProof"><strong>Key Responsibilities</strong></div>
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<div><strong>Technical Leadership:</strong> Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition.</div>
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<div class="elementToProof">    <span class="Apple-converted-space"> </span><em> <span class="Apple-converted-space"> </span></em><strong><em>SOC clocking , FEV/VCLP specialized skills are preferred.</em></strong></div>
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<li><strong>Complex Block/Sub-chip Ownership:</strong> Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the design.</li>
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<div class="elementToProof"><strong>Timing & PPA Strategy:</strong> Act as the primary architect for PD convergence. Derive and implement custom "PPA recipes" that go beyond standard vendor flows to meet aggressive targets.</div>
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<li><strong>Advanced Automation:</strong> Drive efficiency across the team by developing sophisticated<span class="Apple-converted-space"> </span><strong>Tcl and Python</strong> scripts for flow automation, data mining, and sign-off verification.</li>
<li><strong>Stakeholder Management:</strong> Build strong rapport with RTL, DFT, and Synthesis teams. Effectively communicate risks and push for "left-shift" optimizations to safeguard the project schedule.</li>
<li><strong>Sign-off Accountability:</strong> Ensure the sub-chip meets all gold-standard sign-off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).</li>
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<div class="elementToProof"><strong>Technical Requirements</strong></div>
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<div class="elementToProof"><strong>Category</strong></div>
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<div class="elementToProof"><strong>Requirement</strong></div>
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<div class="elementToProof"><strong>Experience</strong></div>
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<div class="elementToProof">Staff 8-10 years
<div class="elementToProof">Senior Staff 11-13 years</div>
PD experience with a proven track record of multiple successful<span class="Apple-converted-space"> </span><strong>lead-level</strong> tape-outs.</div>
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<div class="elementToProof"><strong>Tool Mastery</strong></div>
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<div class="elementToProof">Expert-level proficiency in<span class="Apple-converted-space"> </span><strong>Cadence Innovus/Tempus</strong></div>
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<div class="elementToProof"><strong>Timing Convergence</strong></div>
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<div class="elementToProof">Deep expertise in Static Timing Analysis (STA), including complex clocking, multi-corner sign-off, and crosstalk closure.</div>
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<div class="elementToProof"><strong>PPA Optimization</strong></div>
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<div class="elementToProof">Demonstrated ability to squeeze performance out of advanced nodes (7nm, 5nm, or below) via custom floorplanning, CTS strategies and other convergence approaches.</div>
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<div class="elementToProof"><strong>Automation</strong></div>
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<div class="elementToProof">Advanced scripting in<span class="Apple-converted-space"> </span><strong>Tcl and Python</strong> to build scalable, repeatable design methodologies.</div>
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<div class="elementToProof"><strong>Leadership & Soft Skills</strong></div>
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<li><strong>High Workability & Assertiveness:</strong> You are a proactive communicator who can hold ground on technical requirements while remaining collaborative and solution-oriented.</li>
<li><strong>Analytical Problem Solver:</strong> You don't just identify violations; you analyze the "why" and derive a systemic fix that prevents the issue from recurring.</li>
<li><strong>Driven & Versatile:</strong> You possess the "Senior Staff" mindset—ready to jump into any part of the flow (from floorplan to GDSII) to unblock the team and meet the schedule.</li>
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<div><strong>Mentorship:</strong> Passionate about raising the technical bar for the engineers reporting to you.</div>
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