Staff/Principal ATE Test Engineer

<div class="content-intro"><p>Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. By driving down the cost and complexity of power delivery and leveraging innovative hardware and software, the company seeks to decrease energy consumption, optimize power delivery, increase compute performance, and maximize the efficiency of AI operations.</p></div><p><span class="TextRun SCXW164883129 BCX4" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW164883129 BCX4">Staff/</span><span class="NormalTextRun SCXW164883129 BCX4">Principal<span class="Apple-converted-space"> </span></span><span class="NormalTextRun SCXW164883129 BCX4">ATE</span><span class="NormalTextRun SCXW164883129 BCX4"><span class="Apple-converted-space"> </span>Test Engineer</span></span><span class="EOP SCXW164883129 BCX4" data-ccp-props="{}"> </span></p>
<p><strong>About The Team</strong></p>
<p>We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking.  Our response is never “no, but….” instead “yes, if….”.  We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.</p>
<p><strong><span data-contrast="none">Location:</span></strong><span data-contrast="none"> Minimum of 3 days a week in the office in Torrance, CA.  </span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="none">About The Role</span></strong><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="none">We are seeking a highly experienced Principal ATE Test Engineer to lead test development and production test strategy for a high-performance integrated voltage regulator (IVR) semiconductor product line targeting advanced AI and HPC power delivery applications.</span><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="none">This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and manufacturing optimization. The ideal candidate combines deep technical expertise in mixed-signal and power semiconductor test with strong leadership across silicon bring-up and high-volume manufacturing environments.</span><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="none">The candidate is expected to operate as a senior technical leader capable of driving test strategy independently across internal teams and external manufacturing partners. </span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="none">What You Will Do</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Define overall manufacturing test strategy for IVR silicon across wafer probe and package final test</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Develop production screening methodologies for:</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Analog and mixed-signal circuits</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Integrated ADCs and telemetry</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Digital control and state machines</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">PMBus/I2C interfaces</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">OTP/eFuse programming</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Protection and fault-management circuitry</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Power-stage functionality and efficiency</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Partner with Design and DFT teams to ensure robust testability and manufacturability</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Lead development of wafer sort and final test solutions on production ATE platforms, including:</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">ATE Test programs</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Probe/load board hardware</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Calibration methodologies</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Thermal management approaches</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Multisite test architectures</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Drive aggressive test time reduction while maintaining production quality targets.</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Support transition from engineering characterization flows into scalable high-volume production test</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Support first-silicon bring-up activities and debug of manufacturing test flows</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Support trim development, calibration algorithms, and production limit setting</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Debug silicon, hardware, and software issues observed during characterization and manufacturing ramp</span><span data-ccp-props="{"335559739":0}"> </span></li>
</ul>
<p><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="none">What You Bring</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li><span data-contrast="none">10+ years in the semiconductor industry, with a proven track record developing manufacturing test solutions for high-volume semiconductor products.</span><span data-ccp-props="{}"> </span></li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">BS/MS in Electrical Engineering or related field</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Experience with mixed-signal and/or power management IC MFG test development</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Strong understanding of:</span><span data-ccp-props="{"335559739":0}"> </span></li>
</ul>
<ul>
<li>
<ul>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">Wafer probe and final test flows</span> </li>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">Mixed-signal ATE methodologies</span> </li>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">Yield analysis and characterization</span> </li>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">Test hardware development</span> </li>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">Test time optimization</span> </li>
<li data-leveltext="o" data-font="Courier New" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":1440,"335559991":360,"469769226":"Courier New","469769242":[9675],"469777803":"left","469777804":"o","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="2"><span data-contrast="none">OSAT manufacturing flows</span><span data-ccp-props="{"335559739":0}"> </span></li>
</ul>
</li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Experience with high-volume semiconductor manufacturing environments</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Strong debugging capability across silicon, hardware, software, and manufacturing domains</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Experience working with foundries and outsourced manufacturing/test partners</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Familiarity with PMBus, I2C, telemetry, and power management architectures</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Experience with Advantest, Teradyne, or Cohu mixed-signal/power ATE platforms</span> </li>
<li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="none">Understanding of DFT methodologies for mixed-signal SoCs</span><span data-ccp-props="{"335559739":0}"> </span></li>
</ul>
<p> </p>
<p><strong><span data-contrast="none">Salary Range</span></strong><span data-contrast="none">: $160k-$200k.  This represents the typical salary range for this position based on experience, skills, and other factors.</span><span data-ccp-props="{}"> </span></p>
<p><span data-ccp-props="{}"> </span></p><div class="content-conclusion"><p><strong><span data-contrast="auto">Our Red Cell Partners Benefits:</span></strong><span data-ccp-props="{"134233117":false,"134233118":false,"335559685":0,"335559738":0,"335559739":0}"> </span></p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Career track opportunity with potential for rapid advancement with strong performance as the firm grows </span><span data-ccp-props="{"201341983":0,"335559