Hardware Engineering Technical Leader
Posted Sep 15, 2026·Open for 7 days (and counting)
Hiring for this role?
Generate a McCoy IQ challenge in 30 seconds.
See how candidates think and approach the work this role demands, before the phone screen. We'll build a video challenge from this posting, and you can edit or share it before it goes live.
Key details
Function
Engineering
Seniority
Manager
Workplace
Hybrid
Location
Taiwan
Specialty
Semiconductor Packaging
Job Description
Seeking a senior leader to drive the design, development, and manufacturing of advanced optical transceivers using silicon photonics packaging. Lead technical teams, optimise high-volume processes, and resolve manufacturing challenges. Ideal for experienced professionals in semiconductor packaging and cross-functional leadership.
Audit details(provenance, verification trail, raw fields)
Core fields
Posting ID
cisco:CISCISGLOBAL2025018EXTERNALENGLOBALTitle
Hardware Engineering Technical Leader
Function
Engineering
Location
Kaohsiung, Kaohsiung City, Taiwan
Workplace mode
hybrid
Posted at
2026-09-15 00:00:00Z
Compensation
undisclosed
Provenance
First seen (our tracker)
2026-09-15 08:35:48Z
Last seen
2026-09-17 08:37:12Z
Last updated
2026-09-17 08:37:12Z
Removed at
still open
Days open
Open for 7 days (and counting)
ATS adapter
phenom
ATS slug
careers.cisco.com|/global/en/search-resultsVerification trail
- unknown2026-09-22 08:34:09Zvia phenom
evidence
{ "ats": "phenom", "reason": "ats_unsupported" }
LLM enrichment
Enriched at 2026-09-15 12:24:00Z. Enrichment runs once per posting, never re-runs.
Seniority
manager_m2
Role archetype
engineering
Specialty
semiconductor_packaging
Workplace mode
hybrid
City (normalized)
Taipei
Country (normalized)
Taiwan
Comp range
—
Tech stack
—
Novel role archetype?
no
See how we measure for definitions, or our corrections log for known issues. Found something wrong? Flag a correction.