This role has been removed. The original listing was at https://jobs.lever.co/CesiumAstro/b73ff523-a1cd-4159-b701-fe5cc3d9b296.
Key details
Function
Engineering
Workplace
On-site
Location
US
Job Description
Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.
At CesiumAstro, we are developers and pioneers of out-of-the-box communication systems for satellites, UAVs, launch vehicles, and other space and airborne platforms. We take pride in our dynamic and cross-functional work environment, which allows us to learn, develop, and engage across our organization. If you are looking for hands-on, interactive, and autonomous work, CesiumAstro is the place for you. We are actively seeking passionate, collaborative, energetic, and forward-thinking individuals to join our team.
We are looking to add a Senior FPGA Engineer II to our team. If you are great at what you do, enjoy working in a startup environment, and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.
In this position, you will be responsible for FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also desirable.
The successful candidate will present engineering design review materials to our customers and executive team, as well as participate in proposal-writing efforts. As such, excellent written and verbal communication skills are required.
Audit details(provenance, verification trail, raw fields)
Core fields
Posting ID
cesiumastro:b73ff523-a1cd-4159-b701-fe5cc3d9b296Title
Senior FPGA Engineer II
Function
Engineering
Location
Westminster, CO
Workplace mode
in_person
Posted at
2025-11-04 20:18:19Z
Compensation
undisclosed
Provenance
First seen (our tracker)
2026-07-20 21:46:42Z
Last seen
2026-07-22 05:10:33Z
Last updated
2026-07-25 05:05:57Z
Removed at
2026-07-25 05:05:57Z
Days open
Open for 262 days
ATS adapter
lever
ATS slug
CesiumAstroVerification trail
- confirmed_closed2026-07-25 05:06:00Zvia lever
evidence
{ "url": "https://api.lever.co/v0/postings/CesiumAstro/b73ff523-a1cd-4159-b701-fe5cc3d9b296", "status": 404 }
See how we measure for definitions, or our corrections log for known issues. Found something wrong? Flag a correction.